The present invention relates to a liquid crystal display device and a driving circuit thereof and, more particularly, to a driving circuit for supplying data outputted from a data line driver to a display area.
An active-matrix type liquid crystal display device, represented by a TFT (Thin Film Transistor) liquid crystal panel, is expected to become widespread as a display device for home use TVs and office automation devices. This is because the active-matrix type liquid crystal display device can be easily made to be thinner and lighter compared with a CRT, with no less high display quality than that of the CRT. Taking advantage of the thin and lightweight features, the device is demanded to be adopted not only to portable information devices such as a notebook personal computer but also to multimedia information devices of various kinds and an improvement in display quality is required for a polysilicon liquid crystal display (LCD) with a narrow frame.
FIG. 1 is a schematic view showing the structure of a liquid crystal display device. A signal source 101 such as a personal computer is connected to a connector 111 in a control circuit 110. The control circuit 110 includes a controller 112, connectors 113 and 114, a ROM 115, a power supply circuit 116, and a switch 117 in addition to the connector 111. The connector 113 in the control circuit 110 is connected to a connector 131 in a PCB (Printed Circuit Board) 130 via data lines (video signal lines) A121 and A122. The connector 114 in the control circuit 110 is connected to the PCB 130 via a control signal line (including a power source line) A123. The PCB 130 has a reference power source 132 in addition to the connector 131. Data on the data lines A121 and A122 is supplied to data line drivers TAB1, TAB2, TAB3, and TAB4 composed by TAB (tape automated bonding) via the connector 131. The data line drivers TAB1, TAB2, TAB3, and TAB4 supply data to a liquid crystal display panel 150.
The liquid crystal display panel 150 includes a scanning line driver 153, TFTs 151, and liquid crystal capacitors 152. The TFTs 151, which control pixels, are two-dimensionally provided. Outputs of the data line drivers TAB1, TAB2, TAB3, and TAB4 are connected to drains of the TFTs via data lines. Outputs of the scanning line driver 153 are connected to gates of the TFTs 151 via scanning lines. One end of each of the liquid capacitors 152 is connected to a source of each of the TFTs 151 and the other ends thereof are connected to a common reference terminal. The TFTs 151 supply data supplied from the data line drivers TAB1, TAB2, TAB3, and TAB4 to the liquid crystal capacitors 152 when the gates thereof are set to a high level. Thereby, the transmittance of the liquid crystal capacitors 152 varies to control the display.
FIG. 2 shows a driving circuit of a block sequential driving method of the prior art. A data line driver 200 corresponds to the data line driver TAB1, TAB2, TAB3, or TAB4 in FIG. 1. In FIG. 2, a part except for the data line driver 200 is a driving circuit and provided on the liquid crystal display panel 150 in FIG. 1.
The data line driver 200 is connected to n pieces of driver output lines OUT1 to OUTn. The n pieces of driver output lines OUT1 to OUTn are respectively connected to n pieces of data buses V1 to Vn.
Control terminals of switches S1 to Sn are connected with a block selection signal line BL1, input terminals thereof are connected with the data buses V1 to Vn respectively, and output terminals thereof are connected with data lines D1 to Dn respectively.
Control terminals of switches Sn+1 to S2n are connected with a block selection signal line BL2, input terminals thereof are connected with the data buses V1 to Vn respectively, and output terminals thereof are connected with data lines Dn+1 to D2n respectively.
Similarly, control terminals of switches S2n+1 to S3n are connected with a block selection signal line BL3 and control terminals of switches S3n+1 to S4n are connected with a block selection signal line BL4.
First of all, the block selection signal line BL1 is set to a high level and the block selection signal lines BL2 to BL4 are set to a low level. Then, the switches S1 to Sn are turned on to connect the input terminals and the output terminals. Accordingly, the driver output lines OUT1 to OUTn are connected to the data lines D1 to Dn respectively. Data outputted from the data line driver 200 is supplied to a display area (including the TFTs 151 and the liquid crystal capacitors 152 in FIG. 1) via the data lines D1 to Dn.
Secondly, the block selection signal line BL2 is set to the high level and the block selection signal lines BL1, BL3, and BL4 are set to the low level. Then, the switches Sn+1to S2n are turned on to connect the input terminals and the output terminals. Accordingly, the driver output lines OUT1 to OUTn are connected to the data lines Dn+1 to D2n respectively. Data outputted from the data line driver 200 is supplied to the display area via the data lines Dn+1 to D2n. 
Thereafter, the operation in which the block selection signal lines BL1 to BL4 are sequentially set to the high level is repeatedly performed. Incidentally, the switches connected to the block selection signal lines BL1 to BL4 are not limited to the those which are turned on at the high level, and logically-reversed switches may be utilized.
In driving the polysilicon LCD of the block sequential driving method using the data line driver 200, since a data voltage from the data line driver 200 is first supplied to the data buses V1 to Vn and then transmitted to the data lines D1 to Dn leading to pixels, a majority intersections are required in a wiring region on the substrate, which causes reduced yield due to a short circuit between lines or the like and ghosts due to wiring cross-talk and loses the display quality.